應用於X頻段通訊雷達收發系統之放大器設計;Amplifier Design for X-Band Communication Radar Transceiver Syatem

NCUIR > College of Electrical Engineering & Computer Science > Executive Master of Communication Engineering > Electronic Thesis & Dissertation > Item 987654321/95337

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/95337

Title:	應用於X頻段通訊雷達收發系統之放大器設計;Amplifier Design for X-Band Communication Radar Transceiver Syatem
Authors:	張耿豪;Chang, Keng-Hao
Contributors:	通訊工程學系在職專班
Keywords:	放大器;低功耗
Date:	2024-07-10
Issue Date:	2024-10-09 16:40:47 (UTC+8)
Publisher:	國立中央大學
Abstract:	本學位論文提出使用於X頻段(9~10 GHz)通訊雷達系統的收發機放大器設計。基於近年物聯網的概念越發普及，多數系統皆需具備通訊功能，因此收發系統的耗電量也越發被重視。有鑒於此，設計方面著重於在提高增益的同時也須降低晶片功耗。本論文研發第一個晶片為用於X頻段發射機的功率放大器設計，此顆晶片為使用穩懋0.15 μm GaN製程所製作的功率放大器，電路採用兩共源極電路串聯的架構增加其增益，其小訊號增益為25 dB，飽和輸出功率超過2 W，中心頻的效率為28%，而晶片面積為2.35×1.75 mm2。本論文研發第二個晶片為用於X頻段接收機的低雜訊放大器設計，此顆晶片為使用穩懋0.15 μm GaAs製程所製作的低雜訊放大器，電路架構採用電流再利用(Current-Reused)，以架構降低其耗電量，電路最大增益為20 dB，雜訊最小值為1.35 dB，量測功耗為24 mW，晶片面積為1.11×1.1 mm2。;Novel designs of transmitting and receiving amplifiers applied for X-band (9~10GHz) radar communications are proposed, investigated, implemented, measured, tested and verified in this thesis. With rapidly growing applications of the Internet of Things (IoT) concept, most applications are equipped with communication functionality, thus emphasizing the importance of power consumption reduction in transceiver systems. Accordingly, the designs proposed in this thesis inevitably focus on increase of power gain with reduction of overall power consumption of a single chip. The first chip designed in this thesis is a power amplifier working in a X-band transmitter. This chip is fabricated using a 0.15 μm GaN process from WIN. The circuit employs a cascade configuration to increase its gain. Its small-signal gain is up to 25 dB, with a saturation output power exceeding 2 W, and the best efficiency is 30%. The chip occupies an area only of 2.35×1.75 mm². The second chip is a low-noise amplifier designed for X-band receivers. This chip is fabricated using a 0.15 μm GaAs process from WIN. The circuit architecture adopts a Current-Reused structure to reduce power consumption. The circuit gain is 20 dB, with a minimum noise figure of 1.5 dB. The measured power consumption is 24 mW, and the chip occupies an area only of 1.11×1.106 mm²
Appears in Collections:	[Executive Master of Communication Engineering] Electronic Thesis & Dissertation

Files in This Item:

File	Description	Size	Format
index.html		0Kb	HTML	27	View/Open

社群 sharing

Loading...